Self-Aanalyzing Memory Word

ABSTRACT

Disclosed herein is a memory system in which sought after keywords will identify their own location by setting a flag bit. The important thing is, keywords may be unstructured, hidden in a sea of words; finding one is equivalent to finding a needle in a haystack. To do so, keywords are given a flag bit that is initialized to zero, but conditionally flips true after running a brief algorithm. Subsequently, flag bits can be analyzed to provide the exact addresses of interesting data in a mass storage, separate from the memory in which text keywords are stored. A method of implementation, but not the only method, is to arrange cells in an integrated circuit to form a ‘word’ of memory, Each word may be structured to hold sought after keywords; it may also have optional ‘state’ data. A global bus enables the specification of any binary function on the keywords by selecting source bits in each word. Then a local interword bus enables a particular bit in the word to be flipped if and only if the selected sources are true. A sequence of bus directives as specified in a ‘wiring’ diagram can generally implement any logic in a reversible way for any number of inputs and outputs. As a result, well hidden information, and solutions to certain special problems become available that otherwise take too long to find.

BACKGROUND OF THE INVENTION

Memory search is an important field under computer technology. What isinvented is a memory word circuit that will identify itself if itcontains chosen information. These memory words have capability toexecute any binary function on their own bits using only a very fewtransistors for each bit. The idea was derived from a study of quantumalgorithms originally intended for quantum searching using ahypothetical quantum computer. The basic method was found to apply toordinary semiconductor memory with potential applications to SearchingKeywords Memory. Other applications include solving a SAT(Satisfyability of Boolean Formulae) Problem and solving a GlobalProperties Coding problem. Microcircuits disclosed below are simple andefficient, enabling an increased density of words. Implementationsgenerally execute any reversible logic on each individual word (inparallel) for any number of inputs and outputs.

Content addressable memory (CAM) system, U.S. Pat. No. 5,438,535,referenced below, depends on addressing, implying certain drawbacks. Inpractice, ordinary CAM requires heavy gate overhead for each cell, andfor each word of memory, because each cell must support mismatch logic,tag generation, gates for masking, gates for data input, gates for dataoutput, arithmetic and a variety of valid bit and miss logic.Furthermore, there must be non-trivial peripheral logic to accomplishmultiple match resolution, masking, and multi write. As a result, CAMcells are much larger than their relatively large cousins, static randomaccess memory cells. Worse, all words switch during usage, and thereforeconsume excessive power; heating is such that very large scaleintegration is virtually impossible. Even though CAM cells are large,CAM ability for self-analysis is highly limited if not zero.

System and method for searching a database using a content-searchablememory, U.S. Pat. No. 5,758,148 aims to increase efficiency by mergingassociative logic with refresh logic. Unfortunately, refresh methods ofthis type may require extra clock cycles that could upset the ability ofdynamic memory to refresh itself properly. Ultimately this approach hasall of the above drawbacks of CAM and then some.

Associative database scanning and information retrieval, U.S. Pat. No.6,711,558 adds to the timing problem by looking specifically at serialdata, which is drastically slower than looking at data in parallel. Itclaims to handle either analog or digital data patterns, which suggestsan approximate matching for sought after information. Hence it couldretrieve the wrong information, just the opposite of what is needed, adeterministic, zero-guesswork approach with ample noise margin.

Inventors Listing of Prior Patents

Relevant Patents

U.S. Pat. No. 5,438,535 Content addressable memory system 1995.

U.S. Pat. No. 5,758,148 System and method for searching a database usinga content-searchable memory 1998.

U.S. Pat. No. 6,711,558 Associative database scanning and informationretrieval 2004.

Other Patents

U.S. Pat. No. 6,862,655 Wide word search using serial match linecomputation in content addressable memory

U.S. Pat. No. 4,760,523 Fast search processor

U.S. Pat. No. 6,587,852 Processing circuit and a search processorcircuit

U.S. Pat. No. 5,237,674 Self identifying scheme for memory moduleincluding circuitry for identfying accessing speed

U.S. Pat. No. 5,598,540 Memory module including read-write memory andread-only configuration memory accessed only sequentially and computersystem using as least one such module

ADVANTAGES OF THE INVENTION

-   -   Self-analyzing memory keywords operate in parallel to discover        well-hidden information in a flash.    -   Such words have the capability of taking a binary function on        their own data. The binary function is specified indirectly by a        user, and establishes the locations of sought after keywords.        Subsequently, by analyzing the flag bits with the equivalent of        a priority encoder, or by readout to a counter, it is easy to        quickly generate addresses within mass storage.    -   Memory words do not require addressing nor do they require        reading and writing.    -   Typical structures, such as alphabetical or numerical order, are        unnecessary.    -   Data finding is exact without the uncertainty of guessing about        addresses.    -   No need for complicated computations between the entered        keywords and the output addresses.    -   Memory cells are simple and will allow significant storage        densities beyond what is now possible in parallel memory word        processing.    -   Implementations with a large number of words are capable of        implementing any logic in a reversible way in each word in        parallel, for any number of inputs and outputs.    -   Because of the above advantages, it may be possible to make        searches more tolerant to human error.

DISADVANTAGES OF THE INVENTION

-   -   Keywords memory has limited ability to be read or to be written        since there is no critical need for addressing capability.        Except for the flags, and optional data outputs, keywords memory        is a type of firmware, somewhat as programmable read only        memory.    -   In large applications, designers must consider the time        necessary to convert flag bits into addresses for external mass        storage, or into other codes of interest. In a worst case,        without priority encoding circuitry, the number of clock cycles        for the conversion could equal the number of flag bits. For        example, a million keywords could require one millisecond        assuming a 1 GHz clock.        How the Invention Works

1. Searching Keywords Memory—How it works can be explained with a simpleexample. Imagine that the code in Table 1 represents three unstructuredkeywords. What the keywords point to is assumed stored in mass storage,separate from keyword memory, and in the same order as they appear inkeywords memory. TABLE 1 Keywords Num1 Num0 0 1 0 0 1 0

Keywords have a built-in flag bit labeled f that is initialized to zeroas in Table 2. TABLE 2 Phrases and Flag Bit Num1 Num0 f 0 1 0 0 0 0 1 00

Assume the keyword you want is 01 but that you do not know where inmemory it is located. The search involves executing a binary function oneach keyword in parallel, and setting the flag if keyword 01 isencountered. The ‘wiring’ diagram in FIG. 1 gives the procedure in thiscase.

The empty bubbles denote unconditional NOT gates; the black dots denotea double-controlled NOT gate. Thus if 010 is input (from top to bottom),the first bubble, an unconditional NOT for Num1, changes this to 110,the double-controlled NOT gate changes the code to 111, and the leftmostbubble changes the code to 011. Note that f is set for the sought afterkeyword. All keywords are restored as well as the flag bits, ready forthe next query. The above procedure is of course applied to each word inparallel.

Advantages of the above system are: (1) Search is done in parallel andis faster than any serial method. (2) Data may be unordered. Thus it ispossible to search for keywords that are neither alphabetical nornumerical. (3) There is no penalty for wide keywords and thus it isconvenient to have far fewer items than some power of two.

If RAM has unordered information, a brute force search in a classicalcomputer would have to search through an exponentially large number ofitems, taking excessive time. Parallel search as above is proportionalto the number of address bits being searched and does not require theusual concepts of addressing.

SAT (Satisfyability of Boolean Formulae) Problem—If the solution to aproblem can be expressed as an arrangement of bits that makes a binaryfunction true, then, in principle, the problem can be solved.Unfortunately, classical computers take too long because the length of atruth table for a function grows exponentially with the number of bits.In the above system such problems are solved fast by letting keywords bebinary numbers. The wiring diagram then executes the appropriatefunction on each number, in parallel. Subsequently, the problemsolution, if there is one, is flagged.

Global Properties Encoding Problem—A binary function has globalproperties, for examples, a balanced number of 1s and 0s in its truthtable, symmetry in the truth table, periodicities in the truth table.Note there are truly a large number of binary functions for a givennumber of bits, so global properties are special. Table 3 shows afunction that has particular global properties. TABLE 3 GlobalProperties N1 N0 f 0 0 0 0 1 1 1 0 1 1 1 0

It is clear to a trained eye that f has multiple levels of anti symmetry(in a block whose size is a power of two, each corresponding term in thebottom half is the opposite of the respective term in the top half).Global properties can be expressed as a code, in the above example thecode for f could be |11>. Classical evaluation of binary functions of alarge number of bits requires exponential work, and takes too long,because the length of a truth table grows as a power of two. However,since the number of steps to evaluate the function in the above systemis proportional to number of address bits, global properties are readilyavailable. By reading out the flag bits, it is easy to identify a globalproperties code in a post-processor.

Consider a wiring diagram like the one in FIG. 1. Binary numbers thatare entered on the left (one number in each word) will generally produceoutputs on the right. Wiring diagram logic can denote any combination ofDouble Controlled NOTs, Single Controlled NOTs, and Unconditional NOTson any bits, on each word in parallel. Outputs are reversible functionsof the inputs. If these particular outputs are applied on the right, andthe wiring diagram runs in reverse, the original inputs result.

If keywords contain addresses, then each keyword can be associated with‘optional’ data attached to the keyword. After running through anarbitrary wiring diagram, addresses become modified. A post processingsystem could place the addresses in numerical order, in which case theoptional data would be scrambled in a certain way. Global properties ofthe scrambled data, useful in solving particular problems, can bedetermined by post processing. This is a generalization of the GlobalProperties Encoding Problem.

Referring to FIG. 2, logical operation within a word can be summarizedas follows: If the signal FM1 is enabled, the data item Q is placed onFM1 bus via the 3-state buffer. If FM2 is also enabled, it willsimilarly activate the FM2bus. Should it happen that FM1 and FM2 bus aretrue while the TO signal is also true, the data item Q is flipped. Thusparticular bits in a word can control the flipping of a specified bit.This capability allows the evaluation of a binary function on thecontents of a word.

In practice, the logical operation of a word is translated into a VLSIimplementation based on transistors as suggested in FIG. 3. FM1busB andFM2busB refer to local active-low interword buses; TO, FM1 and FM2 referto global buses. The logic of its operation is similar to that of FIG.2. To refresh, each cell is flipped twice.

The system as described above performs what may be termed‘double-controlled’ NOTs. The dummy cells labeled DUM0 . . . DUMLprovide a true signal that can be placed on FM1 bus or FM2bus, or both,to effect ‘single-controlled’ NOTs and ‘unconditional’ NOTs.

CONCLUSIONS

Self-analyzing memory words discover well-hidden information fast, in aflash, because they operate in parallel. Such words have the capabilityof taking a binary function of their own contents. The binary functionis specified indirectly by a user, and basically establishes thelocations of sought after words. Subsequently analyzing the flag bitswith the equivalent of a priority encoder, or by readout to a counter,quickly generates an address for additional information in mass storage.

Memory words do not require addressing nor do they require reading orwriting. Typical structures, such as alphabetical or numerical order,are unnecessary. Because words are queried in parallel, the flags appearin a flash if there is a match. Data finding is exact without theuncertainty of guessing adddresses. Complicated computations between theentered keywords and output address an be avoided.

Memory cells are simple and allow significant storage densities beyondwhat is now possible for parallel processors. Implementation depends onvery large scale integration technology whose speed and density oftransistors keep increasing. Although implementation details change, thelogic of a self-analyzing memory word will remain as disclosed herein.

Implementations with a large number of words are capable of implementingany logic in a reversible way for any number of inputs and outputs. Thisopens the door for solving specialized problems similar to those thathave been solved using reversible logic. Because of the aboveadvantages, it should be possible to make searches more tolerant tohuman error.

1. A microcircuit that that stores keywords (addresses) and optional(state) data, that can execute any given binary function on its owncontents and place the result in a flag bit attached to the word. 2.Microcircuits that operate in parallel according to instructions in a‘wiring’ diagram, as generated by sought after keywords, or sought aftersolutions to problems, whose time to evaluate any binary function onitself is proportional to the number of bits in the keyword.
 3. A memorymicrocircuit for massive parallel processing that uses interword buses,transistor switches and cells whose bit value can be flipped, toimplement any logic in a reversible way for any number inputs andoutputs.